1. Technical Field
The present disclosure relates to a semiconductor integrated circuit, and, more particularly, to a semiconductor integrated circuit which reduces a skew between data and a clock signal, and a method for eliminating a skew by using the same.
2. Discussion of Related Art
In serial communication schemes, communication circuits transmit the clock signal together with the data signals. On the other hand, in parallel communication schemes, communication circuits transmit the clock signal separately from the data.
Because the serial communication schemes transmit the clock signal along with the data, a serial interface on the receiving end uses a clock data recovery scheme (“CDR”) to extract the clock signal from the received data. In addition, the CDR scheme also eliminates any skew between the clock signal and the received data. To this end, in the CDR scheme, a clock signal tracks any variation occurring in the data during data transmission so as to help maintain a suitable sampling position. Furthermore, the CDR scheme also ensures that the data transmission and reception operation is not affected by any variation in temperature or voltage. In addition, in a CDR scheme, a clock signal to be used for sampling (“sampling clock”) is extracted from data.
While the above-mentioned features of a CDR scheme make it an attractive choice in the field of serial communications, the CDR scheme suffers from several limitations such as, for example, an increased circuit area.
FIG. 1 is a schematic waveform diagram illustrating a basic principle of a conventional CDR scheme. Referring to FIG. 1, clock data (Clk_data) and a clock edge (Clk_edge) are spaced at a half period. In particular, the clock data (Clk_data) is part of a clock signal for identifying data, and the clock edge (Clk_edge) is another part of the clock signal for extracting data edge information.
For example, when the data is changed from logic 0 to logic 1 and from logic 1 to logic 0, a phase relationship between the data and the clock signal can be obtained using the clock edge (Clk_edge). Furthermore, the above-described CDR scheme is called an ×2 oversampling scheme because data is obtained twice in one period.
In the CDR scheme, the clock signal tracks data variation even during data transmission so that a suitable sampling position is maintained. Accordingly, temperature variation or voltage variation does not affect data transmission.
However, the CDR scheme requires a separate receiving circuit for identifying a clock edge (Clk_edge), data, and a sampling clock and detecting an edge of the data, and a separate phase control circuit for changing the phase of the clock. This requirement of two separate circuits in a CDR scheme leads to an increased area requirement for a CDR scheme. Accordingly, the CDR scheme is difficult to use in a parallel communication scheme that is used in, for example, a DRAM.
Instead, in parallel communication schemes, per-pin skew calibration may be used to eliminate the skew between a received clock signal and received data. In particular, there exists a training-based per-pin skew calibration scheme that exhibits substantially the same skew eliminating effect as the CDR scheme, but requires a smaller area. That is, unlike the CDR scheme, the training-based per-pin skew calibration scheme does not require a separate data edge detection circuit in a receiving circuit. This per-pin skew calibration scheme which is used mainly in a semiconductor memory device such as a DRAM will now be described with reference to FIG. 2.
FIG. 2 is a schematic waveform diagram illustrating a conventional per-pin skew calibration scheme. Generally, in the per-pin skew calibration scheme, phase shift is performed by a memory controller, and not by a semiconductor memory device.
First, data is stored at a low frequency in the semiconductor memory device. Then, in a data read operation, the data is read with a per-pin clock phase of the controller shifted by one step for per-pin skew calibration. The phase step shift is for periodically determining whether the read data has an error. In this case, by detecting a phase in which an error (i.e., fail (F)) is generated, it is possible to determine a phase in which the error is least likely to be generated (i.e., pass (P) is most likely to occur). The same method is used during a data write operation to adjust the data phase of each pin.
While the per-pin skew calibration scheme uses less area than a CDR scheme, the per-pin skew calibration scheme consumes more time than the CDR scheme to perform one operation. Accordingly, frequent operation of the system may degrade system performance. Furthermore, periodic calibration is required because the operation speed decreases in actual chip operation and a skew varies with temperature or voltage variation.
There is therefore a need for skew elimination circuits and methods that use less area and also have higher operating speeds without the need for frequent calibration. The present disclosure is directed towards such skew elimination circuits and methods.